Ping Lu
Titel
Forskare
Organisation
046-2223450
Ping [dot] Lu [at] eit [dot] lth [dot] se
Publikationer (hämtat ur Lunds universitets publikationsdatabas)
författare
- 2013
- 2012
- A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
- A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
- A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
- A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
- 2011
- A 0.13µm CMOS ΔΣ PLL FM Transmitter
- A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
- A 5GHz 90-nm CMOS all digital phase-locked loop
- A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
- A Digital PLL with a Multi-Delay Coarse-Fine TDC
- A mixed mode design flow for multi GHz ADPLLs
- 2010
- 2009
- 2008
- 2007
- 2006
- A 12-bit 125-MHz segmented current-steering DAC for communication application
- A 4.6GHz PLL with automatic frequency calibration based on multiple-pass ring oscillator
- A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet
- A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet
- 2005
- A 1.8V transmitter for 10/100 Mbps Ethernet physical layer
- A 1.8v low-jitter clock generator for 1000 Base-T Ethernet Transceiver
- A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver
- A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver
- Delay-locked loop and its applications
