Viktor Öwall
Titel
Professor
Organisation
046-2229469
0709 - 22 37 87
Viktor [dot] Owall [at] eit [dot] lth [dot] se
Publikationer (hämtat ur Lunds universitets publikationsdatabas)
författare
- 2013
- A 0.8mm2 9.6mW Implementation of a Multicarrier Faster-Than-Nyquist Signaling Iterative Decoder in 65nm CMOS
- A 0.8mm2 9.6mW Iterative Decoder for Faster-than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65nm CMOS
- A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures
- Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
- Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
- Hardware architecture of IOTA pulse shaping filters for multicarrier systems
- VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems
- 2012
- A receiver architecture for devices in wireless body area networks
- Energy Efficient MIMO Channel Pre-processor Using a Low Complexity On-Line Update Scheme
- High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
- Mapping Channel Estimation and MIMO Detection in LTE-Advanced on a Reconfigurable Cell Array
- Selective Channelization on an SDR Platform for LTE-A Carrier Aggregation.
- 2011
- An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- Analysis of a novel low complex SNR estimation technique for OFDM systems
- Complexity analysis of IOTA filter architectures in Faster-than-Nyquist multicarrier systems
- Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier systems
- Guest Editorial
- Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder
- Multicarrier faster-than-Nyquist transceivers: hardware architecture and performance analysis
- Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping
- Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
- 2010
- A <1 pJ sub-VT Cardiac Event Detector in 65 nm LL-HVT CMOS
- A low power analog channel decoder for ultra portable devices in 65 nm technology
- A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM
- An iterative decoder for multicarrier Faster-than-Nyquist signaling systems
- Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
- Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding
- Low power analog channel decoder in sub-threshold 65nm CMOS
- Performance analysis of sign-based pre-FFT synchronization in OFDM systems
- Reconfigurable cell array as enabler for supporting concurrent multiple standards in mobile terminals
- 2009
- A Hardware Architecture for Real-Time Video Segmentation Utilizing Memory Reduction Techniques
- A Transmitter Architecture for Faster-than-Nyquist Signaling Systems
- A coarse-grained dynamically reconfigurable architecture for digital signal processing
- An architecture for calculation of the distance transform based on mathematical morphology
- Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture
- Design of coarse-grained dynamically reconfigurable architecture for DSP applications
- Energy efficient biomedical signal processing in implantable devices
- Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter
- Sign-Bit based architecture for OFDM acquisition for multiple-standards
- 2008
- A generic hardware MAC for wireless personal area network platforms
- A hardware acceleration platform for digital holographic imaging
- A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing
- A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
- An Embedded Real-Time Surveillance System: Implementation and Evaluation
- Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements
- Modeling and exploration of a reconfigurable architecture for digital holographic imaging
- Modelling and exploration of a reconfigurable array using SystemC TLM
- Optimization and implementation of a Viterbi decoder under flexibility constraints
- Reducing computational complexity of branch metric calculations in a trellis decoder
- 2007
- Accelerating vector operations by utilizing reconfigurable coprocessor architectures
- Implementation of a labeling algorithm based on contour tracing with feature extraction
- Implementing the G.723.1 speech codec using a coarse-grained reconfigurable coprocessor
- Low Complexity Real-Time Feature Extraction Using Image Projections
- Survivor path processing in Viterbi decoders using register exchange and traceforward
- 2006
- Architectural Optimization for Low power in a Reconfigurable UMTS filter
- Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores
- Background segmentation beyond RGB
- FPGA Implementation of Real-Time Video Segmentation with GMM Model
- Hardware aspects of a real-time surveillance system
- Hardware aspects of a real-time surveillance system
- Implementation of a Connected-cluster Labeling Algorithm Based on Contour Tracing
- Leakage Minimization in Cardiac Rhythm Management Devices by Time-multiplexing
- Real-time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction
- 2005
- A Computational Platform for Real-time Channel Measurements using the Capon Beamforming Algorithm
- A Soft Output Sphere Decoder for MIMO Systems
- A Streaming Hardware Accelerator for Digital Holography
- A dual-mode wavelet based R-wave detector using single-V<sub>t</sub> for leakage reduction cardiac pacemaker applications
- A hardware efficiency analysis for simplified trellis decoding blocks
- A low complexity architecture for binary image erosion and dilation using structuring element decomposition
- A manual on ASIC front to back end design flow
- A scalable pipelined complex valued matrix inversion architecture
- Architectural considerations for rate-flexible trellis processing blocks
- Area and power efficient trellis computational blocks in 0.13μm CMOS
- Compact Matrix Inversion Architecture Using a Single Processing Element
- Digital implementation of a wavelet-based event detector for cardiac pacemakers
- Fixed-point implementation of a robust complex valued divider architecture
- Hardware accelerator design for video segmentation with multi-modal background modelling
- Implementation Aspects for Flexible Viterbi Decoders
- Implementation Aspects for a Reconfigurable Application-Specific Accelerator
- Implementation aspects of a novel speech packet loss concealment method
- Teaching digital ASIC design to students with heterogeneoms previous knowledge
- Teaching digital ASIC design to students with heterogeneous previous knowledge
- XStream - A Hardware Accelerator for Digital Holographic Imaging
- 2004
- A Method for Packet Loss Concealment of Speech
- A Reconfigurable System for Image Reconstruction in Digital Holography
- A flexible wavelet filter structure for cardiac pacemakers: a power efficient implementation
- A simplified computational kernel for trellis-based decoding
- A wavelet based R-wave detector for cardiac pacemakers in 0.35 CMOS technology
- Computional Challenges in Digital Holography
- Controller Synthesis in Hardware Accelerator Design for Video Segmentation
- FPGA implementation of controller-datapath pair in custom image processor design
- Implementation of a Full Matrix Inversion Architecture for Adaptive Antenna Algorithms
- On Complexity Reduction in Trellis Computational Kernels
- On VLSI Implementations of MIMO Detectors for Future Wireless Communications
- Power optimization of a reconfigurable FIR-filter
- Xilinx Virtex II Pro implementation of a reconfigurable UMTS digital channel filter
- 2003
- A 2048 complex point FFT processor using a novel data scaling approach
- A Pre-Study of Design Space Exploration for Hardware-Software Systems
- A configurable divider using digit recurrence
- Accelerating signal processing algorithms in digital holography using an FPGA platform
- Channel Coding in a Varying Environment
- Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm
- Design and ASIC Performance Analysis of a Reconfigurable Digital Filter for a UMTS Application
- FPGA Implementation of Controller-Datapath Pair in Custom Image Processor Design
- FPGA implementation of real-time image convolutions with three level of memory hierarchy
- Implementation of a Highly Scalable Architecture for Fast Inversion of Triangular Matrices
- Implementation of a Scalable Matrix Inversion Architecture for Triangular Matrices
- Power aware communications for wireless OptiMised personal area network
- Providing flexibility in a convolutional encoder
- Teaching digital HW-design by implementing a complete MP3 decoder
- 2002
- A Pipelined FFT Processor using Data Scaling and Reduced Memory Requirements
- A new System-on-Chip Curriculum at Lund University
- Alternative Hardware Implementation of the Tailbiting BCJR Decoder
- Architectural tradeoffs for a custom implementation of an acoustic echo canceller
- Controller Synthesis for Hardware Accelerator Design
- Optimised QR-Decomposition Core for Adaptive Beamforming
- R-wave detection for pacemakers using a matched filter based on an artificial neural network
- 2001
- 2000
- 1999
- 1998
- A complex multiplier with low logic depth
- A low logic depth complex multiplier
- Detectors Based on Non-Decision Directed Interference Cancellation in a Hardware Implementation Perspective
- Hardware Implementation Aspects of a Detector Based on Successive Interference Cancellation in a DS/CDMA System
- Interference cancellation detectors in a hardware implementation perspective
- 1997
- 1996
- 1995
- 1994
- 1993
- 1991
