Jiren Yuan
Titel
Professor emeritus
Organisation
046-2224888
Jiren [dot] Yuan [at] eit [dot] lth [dot] se
Publikationer (hämtat ur Lunds universitets publikationsdatabas)
författare
- 2007
- A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS
- A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references
- A digital-baseband mixed-signal chip for ultra wide band applications
- A low complexity DDS IC for FM-UWB applications
- Calibration technique for op-amp finite gain in pipelined ADC
- 2006
- 2005
- A 1 GHz CMOS current-folded direct digital RF quadrature modulator
- A Reconfigurable Pipelined ADC in 0.18 um CMOS
- Accurate sample-and-hold circuit model
- Design considerations of a floating-point ADC with embedded S/H
- Performance analysis of general charge sampling
- Silent CMOS circuits aiming for system-on-chip
- Studies of time error limitations in ADC systems with random parallel passive sampling
- 2004
- A CMOS 500 MS/S charge sampler
- A CMOS 500 MS/s charge sampler
- A CMOS charge sampler with amplification function
- A Novel Reconfigurable Pipelined A/D Conversion Technique for Multistandard Wideband Receivers
- A novel reconfigurable pipelined A/D conversion technique for multistandard wideband receivers
- A programmable analog-to-digital converter
- A simulation model for embedding the transistor bias
- A single-stage direct interpolation multiphase clock generator with phase error averaging
- An accurate circuit model for a general sample-and-hold circuit
- Distortion in pipelined analog-to-digital converters
- Low power very fast dynamic logic circuits
- 2003
- A 10-bit wide-band CMOS direct digital RF amplitude modulator
- A 8-bit 100-MHz CMOS linear interpolation DAC
- A 80 dB second order - modulator
- A differential difference comparator for multi-step A/D converters
- A highly integrated CMOS direct digital RF quadrature modulator
- A silent CMOS circuit technique
- An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average
- Charge sampling analogue FIR filter
- On the effects of static errors in a pipelined A/D converter
- Performance analysis of general charge sampling
- 2002
- A 10-bit, 100-MHz CMOS linear interpolation DAC
- A CMOS analog FIR filter with low phase distortion
- A direct digital RF amplitude modulator
- A low distortion wide band CMOS direct digital RF amplitude modulator
- A non-feedback multiphase clock generator
- A non-feedback multiphase clock generator using direct interpolation
- A single-stage direct interpolation multiphase clock generator with phase error average
- 2001
- 2000
- A charge sampling mixer with embedded filter function for wireless applications
- A sampler with embedded filter function
- Accurate sampling of radio signals beyond gigahertz in CMOS
- An 8-bit, 100 MHz low glitch interpolation DAC
- Analysis and implementation of a semi-integrated Buck converter with static feedback control
- Comparison of charge sampling and voltage sampling
- Single input current-sensing differential logic (SCSDL)
- 1999
- 1997
- 1995
- 1994
- A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-um CMOS
- A 3-level asynchronous protocol for a differential two-wire communication link
- High speed CMOS subsystems
- High speed circuit techniques for pipelining and for one clock-cycle decision
- Ultimate CMOS speed and device sizing
- 1993
- 1991
- 1989
- 1988
- 100-400 Mhz digital and analog technique in 3 um CMOS process
- A CMOS implementation of a video-rate successive approximation A/D converter
- A phase-shifting PLL frequency offseter
- Bit-serial realization of maximum and minimum filters
- CMOS circuit speed optimization based on switch level simulation
- Efficient CMOS counter circuits
- 1987
