Peter Nilsson

författare

• 2013
  • VLSI Implementation of a Soft-Output Signal Detector for Multi-Mode Adaptive MIMO Systems
• 2012
  • A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
  • A receiver architecture for devices in wireless body area networks
  • A unified multi-mode MIMO detector with soft-output
  • Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes
  • High Current Density InAsSb/GaSb Tunnel Field Effect Transistors
  • High-Performance InAs Nanowire MOSFETs
  • High-performance 15 nm diameter InAs nanowire Ω-gate MOSFETs
  • Low complexity likelihood information generation for spatial-multiplexing MIMO signal detection
  • Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
• 2011
  • A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm
  • Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
  • Detecting multi-mode MIMO signals: algorithm and architecture design
  • Improved matching pursuit algorithm and architecture for LTE channel estimation
  • Improved matching pursuit algorithm and architecture for LTE channel estimation
  • Inverter circuits based on vertical InAs nanowire MOSFETs
  • Low Complexity Soft-Output Signal Detector for Spatial-Multiplexing MIMO System
  • On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems
  • Power reductions in unrolled CORDIC architectures
  • Ultra low power hardware for computing squared euclidean distances
  • Unified multi-mode signal detector for LTE-A downlink MIMO system
  • Unified signal detector for multi-mode MIMO system
• 2010
  • Bit-Serial CORDIC: Architecture and Implementation Improvements
  • Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
  • On MB OFDM-UWB channel estimation
  • On MB OFDM-UWB channel estimation
  • Parabolic synthesis methodology
  • Power consumption in digital filter architectures in 65 nm CMOS technology
  • Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
  • Vertical InAs nanowire wrap gate transistors for integration on a Si platform
• 2009
  • A methodology for parabolic synthesis
  • A study on leakage minimization by RBB in 65 nm CMOS
  • Architectures and arithmetic for low static power consumption in nanoscale CMOS
  • Complexity Reductions in Unrolled CORDIC Architectures
  • Hardware architecture of an SVD based MIMO OFDM channel estimator
  • Implementation of an SVD Based MIMO OFDM channel estimator
  • On LTE channel estimation architectures
  • Parabolic synthesis methodology implemented on the sine function
• 2008
  • A methodology for arithmetic reduction of the static power consumption verified on filter architectures
  • A methodology for parabolic synthesis of unary functions for hardware implementation
  • An Embedded Real-Time Surveillance System: Implementation and Evaluation
  • Arithmetic reduction of adder leakage in nanoscale CMOS
  • On MIMO K-best sphere detector architecture complexity reductions
  • On MIMO OFDM channel estimation architecture considerations
• 2007
  • A digital-baseband mixed-signal chip for ultra wide band applications
  • A low complexity DDS IC for FM-UWB applications
  • Arithmetic and Architectural Design to Reduce Leakage in Nano-Scale Digital Circuits
  • Hardware architecture for matrix factorization in MIMO receivers
  • Low Complexity Real-Time Feature Extraction Using Image Projections
  • On Leakage Reduction in Nanoscale CMOS Arithmetic
  • On MIMO OFDM Receiver Optimization
  • Reducing Leakage Power in Fixed Coefficient Arithmetic
• 2006
  • A VLSI architecture of the square root algorithm for V-BLAST detection
  • Algorithm and implementation of the K-best sphere decoding for MIMO detection
  • Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS
  • Background segmentation beyond RGB
  • Hardware aspects of a real-time surveillance system
  • Hardware aspects of a real-time surveillance system
• 2005
  • A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS
  • A Low Complexity Soft-Output MIMO Decoding Algorithm
  • A Low-Complexity High-Throughput Soft-Output MIMO Decoder
  • A Soft Output Sphere Decoder for MIMO Systems
  • A low complexity architecture for binary image erosion and dilation using structuring element decomposition
  • Design and implementation of reciprocal unit
  • Effects of lattice reordering on Schnorr-Euchner decoding algorithms for MIMO systems
  • VLSI architecture of the soft-output sphere decoder for MIMO systems
• 2004
  • A Survey of Various Discrete Transforms Used in Digital Image Compression Algorithms
  • A V-BLAST Detector Based on Square Root Algorithm
  • A VLSI architecture of the Schnorr-Euchner decoder for MIMO systems
  • A digitally controlled PLL for SoC applications
  • A low-complexity method for distributed clocking on digital ASICs
  • An ASIC Implementation for V-BLAST Detection in 0.35um CMOS
  • An improved MIMO detector for high data rates wireless communications
  • Bidirectional FFT Processor for OFDM
  • On VLSI Implementations of MIMO Detectors for Future Wireless Communications
  • Reduced complexity Schnorr-Euchner decoding algorithms for MIMO systems
  • Reduced transceiver-delay for OFDM systems
  • VLSI implementation issues of lattice decoders for MIMO systems
• 2003
  • A Generic Transmitter for Wireless OFDM Systems
  • A VLSI implementation of MIMO detection for future wireless communications
  • A digitally controlled PLL for digital SOCs
  • A low-complexity VLSI architecture for square root MIMO detection
  • Event driven design methodology for hardware DSP design
  • Flexible baseband transmitter for OFDM
  • Hardware Architecture for Power Efficient and Portable UMTS Turbo Decoder
  • On VLSI Implementation of Square Root Algorithm for MIMO Detection
  • Portable digital clock generator for digital signal processing applications
  • Teaching digital HW-design by implementing a complete MP3 decoder
• 2002
  • A Flexible FFT Processor
  • A PLL Clock Multiplier Made from Digital Standard Cells
  • A new System-on-Chip Curriculum at Lund University
  • An all-digital PLL clock multiplier
  • Implementation Aspects of High Throughput Iterative Decoders
  • On Detection Algorithms and Hardware Implementations for V-BLAST
• 2001
  • A Digital PLL Made from Standard Cells
  • A fully Integrated Standard-Cell Digital PLL
  • Application of Software Design Patterns to DSP Library Design
  • Design patterns for hardware datapath library design
  • Dual Supply-Voltage Scaling for Reconfigurable SoCs
  • Socware: A New Swedish Design Cluster for System-on-Chip
• 2000
  • A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
  • An OFDM Timing Synchronization ASIC
• 1999
  • A Digitally Controlled On-Chip Clock Multiplier for Globally Asynchronous Locally Synchronous Systems
  • Design of a High Throughput Serial Concatenated Convolution Decoder
  • Globally Asynchronous Locally Synchronous Architecture for Large High-performance ASICs
  • Hardware implementation of an OFDM synchronizer
  • Hardware implementation of an OFDM synchronizer
  • High bandwidth iterative decoding in a fading environment
  • Implementation of an OFDM Synchronization Algorithm
  • Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style
  • Power Reduction in Custom CMOS Digital Filter Structures
  • Silicon realization of an OFDM synchronization algorithm
  • Wordlength Optimization of a Pipelined FFT Processor
• 1998
  • Detectors Based on Non-Decision Directed Interference Cancellation in a Hardware Implementation Perspective
  • Hardware Implementation Aspects of a Detector Based on Successive Interference Cancellation in a DS/CDMA System
  • Interference cancellation detectors in a hardware implementation perspective
  • Word length optimization of an 8k points FFT
• 1997
  • A Custom Digital Intermediate Frequency Filter for the American Mobile Telephone System
  • Coefficient Optimization for Low Power Digital Filters
  • Implementation of Low Power Lattice Wave Digital Filters
  • Low Power Lattice Wave Digital Bit-Serial Filters
  • Low Power Optimization of Bit-Serial Digital Filters
• 1996
  • A Bit-Serial Implementation of a Wavelet Filter-Bank
  • A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's
  • Custom Designed Digital Signal Processors Using Bit-Serial Arithmetic
  • Design of a Fast and Area Efficient Filter
  • Digital channel filters for wideband transceivers
• 1995
  • Custom DSP Design of a GSM Speech Coder
  • Method to Save Silicon Area by Increasing the Filter Order
• 1994
  • A bit-serial CMOS digital IF-filter for mobile radio using an on-chip clock
  • Bit-Serial CMOS Digital IF-Filter for Mobile Radio using an On-Chip Clock
  • Some Experiences from Automatic Synthesis of Digital Filters
• 1993
  • A Bit-Serial Realization of a Lattice Wave Digital Intermediate Frequency Filter
  • A CMOS Digital IF-Filter for Mobile Radio Applications using an On Chip Clock
  • A GSM speech coder implemented on a customized processor architecture
  • A High Performance Bit-Serial Lattice Wave Digital Intermediate Frequency Filter Chip
  • A lattice wave digital intermediate frequency filter
  • CMOS On-Chip Clock for Digital Signal Processors
  • Custom DSP design of a GSM speech coder
  • Custom DSP implementation of a GSM speech coder
• 1992
  • A CMOS VLSI Cell Library for Digital Signal Processing
  • Implementation of a Digital MF-Filter
• 1990
  • A CMOS VLSI Cell Library for Digital Signal Processors
• 1988
  • Testkretsar i CMOS-teknik