Joachim Rodrigues
Titel
Biträdande Lektor
Organisation
046-2224868
0705-220423
Joachim [dot] Rodrigues [at] eit [dot] lth [dot] se
Publikationer (hämtat ur Lunds universitets publikationsdatabas)
författare
- 2013
- 2012
- A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
- A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
- A receiver architecture for devices in wireless body area networks
- High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
- IR-Drop Reduction in Sub-VT Circuits by De-synchronization
- Integration of Full-Custom Cells in a Standard-Cell Based Flow
- När blir man "självständig" forskare vid LTH?
- Sizing of Dual-VT Gates for Sub-VT circuits
- Sub-VT Design of a Wake-up Receiver Back-end in 65 nm CMOS
- TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
- Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
- Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation
- 2011
- A GALS ASIC implementation from a CAL dataflow description
- Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
- Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- Developing independence as young academics at LTH
- Energy-minimum sub-threshold self-timed circuits using current sensing completion detection
- Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection
- Highly Scalable Implementation of a Robust MMSE Channel Estimator for OFDM Multi-Standard Environment
- Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
- Low Power and Area Efficient Implementation of a Real-Time AF Detection Algorithm in 130 nm CMOS
- Physical implementation of analog circuits assisted by conventional digital place and route methods
- Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping
- Synthesis Strategies for Sub-VT Systems
- 2010
- A <1 pJ sub-VT Cardiac Event Detector in 65 nm LL-HVT CMOS
- A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM
- Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
- Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding
- Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS
- Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication
- Minimum-energy sub-threshold self-timed circuits: design methodology and a case study
- Power consumption in digital filter architectures in 65 nm CMOS technology
- Reconfigurable cell array as enabler for supporting concurrent multiple standards in mobile terminals
- Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
- 2009
- 2008
- 2006
- 2005
- A dual-mode wavelet based R-wave detector using single-V<sub>t</sub> for leakage reduction cardiac pacemaker applications
- A manual on ASIC front to back end design flow
- Development and Implementation of Cardiac Event Detectors in Digital CMOS
- Digital implementation of a wavelet-based event detector for cardiac pacemakers
- Teaching digital ASIC design to students with heterogeneoms previous knowledge
- Teaching digital ASIC design to students with heterogeneous previous knowledge
- 2004
- 2002
- 2001
