Henrik Sjöland
Titel
Professor
Organisation
046-2229513
Henrik [dot] Sjoland [at] eit [dot] lth [dot] se
Publikationer (hämtat ur Lunds universitets publikationsdatabas)
författare
- 2013
- 2012
- A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
- A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
- A 2.45GHz ultra-low power quadrature front-end in 65nm CMOS
- A 65-nm CMOS 250uW Quadrature LO Generation Circuit
- A 70 and 210 GHz LO Generator in 65nm CMOS
- A High Efficiency 60GHz Power Amplifier in 65nm CMOS
- A receiver architecture for devices in wireless body area networks
- Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
- 2011
- 60GHz Beamforming Receiver Front-End Measurements
- A 0.13µm CMOS ΔΣ PLL FM Transmitter
- A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
- A 13dBm 60GHz-band injection locked PA with 36% PAE in 65nm CMOS
- A 2GHz Tx LO generation circuit with active PPF and 3/2 divider in 65nm CMOS
- A 5GHz 90-nm CMOS all digital phase-locked loop
- A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays
- A 65nm CMOS 282uW 915MHz direct conversion receiver front-end
- A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
- A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
- A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS
- An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- Design and analysis of an ultra-low-power LC quadrature VCO
- Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- Mixed-mode transmitter architectures
- Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
- 2010
- A 175uW 100MHz-2GHz inductorless receiver frontend in 65nm CMOS
- A 24 GHz SOP VCO with 20 % tuning range
- A 24-GHz 90-nm CMOS beamforming receiver front-end with analog baseband phase rotation
- A 4.35-mW +22-dBm IIP3 continuously tunable channel select filter for WLAN/WiMax receivers in 90-nm CMOS
- A 90 nm CMOS 14.5 GHz Injection Locked LO Generator with Digital Phase Control
- A 90 nm CMOS 14.5 GHz injection locked LO generator with digital phase control
- A 90-nm CMOS +11dBm IIP3 4mW dual-band LNA for cellular handsets
- A low power analog channel decoder for ultra portable devices in 65 nm technology
- A technique for improving gain and noise figure of common-gate wideband LNAs
- K-band receiver front-ends in 0.13um CMOS using carrier technology
- Low power multi-band CMOS receiver front-end
- Low-frequency noise in vertical InAs nanowire FETs
- Switched mode transmitter architectures
- Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
- Vertical InAs nanowire wrap gate transistors for integration on a Si platform
- 2009
- A 24 GHz VCO with 20 % tuning range in 130-nm CMOS using SOP Technology
- A 24-GHz Quadrature Receiver Front-end in 90-nm CMOS
- A 5GHz 90-nm CMOS all digital phase-locked loop
- A 65-nm CMOS ultra-low-power LC quadrature VCO
- A PLL based 12GHz LO generator with digital phase control in 90nm CMOS
- A potential transmitter architecture for future generation green wireless base station
- Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters
- Potential Architecture for Future Generation "Green" Wireless Base Station
- Switched mode transmitter architectures
- Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers
- Two 24 GHz Receiver Front-ends in 130-nm CMOS using SOP Technology
- 2008
- 60 GHz 130-nm CMOS Second Harmonic Power Amplifiers
- 60 GHz Second Harmonic Power Amplifiers in 130-nm CMOS
- A 1W Class-D Audio Power Amplifier in a 0.35um CMOS Process
- A 20-GHz 130-nm CMOS Front-End using Baluns on Glass Carrier
- A 24-GHz LC-QVCO in 130-nm CMOS using 4-bit Switched Tuning
- A 25-GHz Differential LC-VCO in 90-nm CMOS
- A 25-GHz Low Phase Noise LC-VCO
- A 30 GHz 90-nm CMOS Passive Subharmonic Mixer with 15 GHz Differential LO
- A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
- A 90nm CMOS UWB LNA
- A Quad-Core 130-nm CMOS 57-64 GHz VCO
- A comparison of polar transmitter architectures using a GaN HEMT power amplifier
- An integrated 3-level fully adjustable PWM class-D audio amplifier in 0.35um CMOS
- Comparing polar transmitter architectures using a GaN HEMT power amplifier
- Two 130nm CMOS class-D RF power amplifiers suitable for polar transmitter architectures
- 2007
- 25 GHz and 28 GHz wide tuning range130 nm CMOS VCOs with ferroelectric varactors
- A 0.25W Class-D Audio Power Amplifier in 0.35um CMOS
- A 0.25W fully integrated class-d audio power amplifier in 0.35 mu m CMOS
- A 26-GHz LC-QVCO in 0.13-um CMOS
- A CMOS power amplifier using ground separation technique
- A GaN HEMT power amplifier with variable gate bias for envelope and phase signals
- A polyphase filter based on CMOS inverters
- An 8-GHz beamforming transmitter IC in 130-nm CMOS
- Beamforming Transmitter IC at 8-GHz in 130-nm CMOS
- Characterization of CMOS Impedance Tuning Unit
- IC-Project and Verification Course: An Integrated Class-D Audio Amplifier
- IC-Project and Verification Course: Teaching Top Down Analog/Mixed Signal Design
- Measured CMOS Reconfigurable Matching Network and its Switched High Quality Capacitor Building Blocks
- Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network
- Measurement Considerations for a Phased Array Beamforming Transmitter
- Measurement Setup for Impedance Tuning Unit Characterization
- Second Harmonic 60-GHz Power Amplifiers in 130-nm CMOS
- Teaching Top Down Design of Analog/Mixed Signal ICs Through Design Projects
- 2006
- 850/900/1800/1900MHz Quad-Band CMOS Medium Power Amplifier
- A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF CMOS
- A 15GHz and a 20GHz Low Noise Amplifier in 90nm RF CMOS
- A 24-GHz Automotive Radar Transmitter with Digital Beam Steering in 130-nm CMOS
- An all-digital ΣΔ--frequency discriminator of arbitrary order
- Antenna Array for a 24-GHz Automotive Radar with Dipole Antenna Element Patches
- Antenna Impedance Tuning Unit for DVB-H Front-End
- Automotive Radar Transmitter at 24-GHz with Digital Beam Steering in 130-nm CMOS
- Full oscillation cycle phase noise analysis of differential CMOS LC oscillators
- Impedance Tuning Unit for DVB-H Front-End
- Monolithic inductor modeling and optimization
- 2005
- A 2.4 GHz CMOS power amplifier using internal frequency doubling
- A 90 nm CMOS 10 GHz beam forming transmitter
- A Class-AB 1.65GHz-2GHz Broadband CMOS Medium Power Amplifier
- A Comparison of Two 10 GHz Beam Forming Transmitters, in 90 nm and 130 nm CMOS
- A distributed capacitance analysis of co-planar inductors for a CMOS QVCO with varactor tuned buffer stage
- A polyphase filter based on CMOS inverters
- An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band
- CMOS antenna tuning unit for 2.4 GHz ISM band
- Differential measurement and parameter extraction of symmetrical inductors
- Dual band ISM 2.4 GHz and 5 GHz finger antenna
- Low power 0.18μm CMOS dual-band front-end
- 2004
- 2003
- A bootstrapping technique to improve the linearity of CMOS passive mixers
- A fully integrated 2.45 GHz 0.25 mu m CMOS power amplifier
- A fully integrated 2.45GHz 0.25um CMOS power amplifier
- A merged CMOS LNA and mixer for a WCDMA receiver
- Low Voltage 1.8GHz CMOS Quadrature Oscillator with Varactor Tuned Buffer Stage
- Low power radio transmitter
- 2002
- 2001
- A 1.8 GHz CMOS VCO with reduced phase noise
- A 2.2 GHz CMOS VCO with inductive degeneration noise suppression
- A 2GHz merged CMOS LNA and mixer for WCDMA
- A filtering technique to lower LC oscillator phase noise
- A filtering technique to lower oscillator phase noise
- Noise optimization of an inductively degenerated CMOS low noise amplifier
- 1999
- 1998
- 1997
- 1996
- 1995
redaktör
- 2010
