Pietro Andreani

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• 2013
  • A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
  • A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2
  • A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
• 2012
  • A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
  • A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
  • A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
  • A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
  • A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
  • A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
  • An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
  • Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
  • Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference
  • Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
• 2011
  • A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
  • A 9-band WCDMA/EDGE transceiver supporting HSPA evolution
  • A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
  • A Digital PLL with a Multi-Delay Coarse-Fine TDC
  • A TX VCO for WCDMA/EDGE in 90 nm RF CMOS
  • A continuous time delta sigma modulator with reduced clock jitter through DSCR feedback
  • A mixed mode design flow for multi GHz ADPLLs
  • Time-variant analysis and design of a power efficient ISM-band quadrature receiver
• 2010
  • A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
  • Impact of MOS threshold-voltage mismatch in current-steering DACs for CT delta-sigma modulators
  • Low power multi-band CMOS receiver front-end
• 2009
  • A compact CMOS MEMS microphone with 66dB SNR
  • A time-variant analysis of fundamental 1/f3 phase noise in CMOS parallel LC-tank quadrature oscillators
  • Analysis and design of a low-power single-stage CMOS wireless receiver
• 2008
  • A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz
  • Analysis and design of a double-quadrature CMOS VCO for subharmonic mixing at Ka-band
  • Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise
  • Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators""
  • Sensitivity degradation in a tri-band GSM BiCMOS direct-conversion receiver caused by transient substrate heating
• 2007
  • 45% Power Saving in a 0.25um BiCMOS 10Gb/s 50Ohm-Terminated Packaged Active-Load Laser Driver
  • A 0.2V, 7.5 uW, 20 kHz Sigma-Delta modulator with 69 dB SNR in 90 nm CMOS
  • A 0.35um 50V CMOS sliding-mode control IC for buck converters
  • A toroidal inductor integrated in a standard CMOS process
  • An analysis of 1/f2 phase noise in bipolar colpitts oscillators (With a digression on bipolar differential-pair LC oscillators)
  • Enhancement of VCO Linearity and Phase Noise by Implementing Frequency Locked Loop
  • Linearity of bulk-controlled inverter ring VCO in weak and strong inversion
• 2006
  • 1/f Noise Characterization in CMOS Transistors in 0.13um Technology
  • A 0.2V 0.44 uW 20 kHz Analog to Digital Sigma-Delta Modulator with 57 fJ/conversion FoM
  • A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance
  • A 240W Monolithic Class-D Audio Amplifier Output Stage
  • A 300 nW, 12 ppm/°C Voltage Reference in a Digital 0.35 um CMOS Process
  • A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO
  • A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers
  • A novel approach to negative feedback in RX front-ends
  • A time-variant analysis of the 1/f2 phase noise in CMOS parallel LC-tank quadrature oscillators
  • Detailed behavioral modeling of bang-bang phase detectors
  • High-level design flow for all-digital PLLs
  • Misconception regarding use of transformer resonators in monolithic oscillators
  • More on the 1/f2 Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillators
  • On the amplitude and phase errors of quadrature LC-tank CMOS oscillators
  • Single-stage low-power quadrature RF receiver front-end: the LMV cell
• 2005
  • A 0.8V, 7uA, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18um CMOS
  • A low-phase-noise wide-band CMOS quadrature VCO for multi-standard RF front-ends
  • A study of phase noise in colpitts and LC-tank CMOS oscillators
  • Determination of over current protection thresholds for class D audio amplifiers
  • Distortion and error reduction in a class D power stage using feedback
  • Efficient performance simulation of class D amplifier output stages
  • Fully integrated 1.7GHz, 188dBc/Hz FoM, 0.8V, 320uW LC-tank VCO and frequency divider
  • Linearity of bulk-controlled inverter ring VCO in weak and strong inversion
  • Numerical effects in time-domain simulations of electronic circuits - a reminder
  • Phase noise analysis and design of a 3-GHz bipolar differential colpitts VCO
  • Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies
  • Spectrum emission considerations for baseband-modeled CALLUM architectures
  • Technology scaling impact on embedded ADC design for telecom receivers
  • Time domain analysis of open loop distortion in class D amplifier output stages
  • Toroidal inductors in CMOS processes
• 2004
  • A circuit technique improving the image rejection of RF front-ends
  • A phase noise analysis of CMOS colpitts oscillators
  • Comparison of the image rejection between the passive and the Gilbert mixer
  • Impact of oscillator power in discrete and continuous time Sigma Delta converters
  • Implementation of the signal component generator of a CALLUM 2 transmitter architecture in CMOS technology
  • Low-phase-error and low-phase-noise 2GHz CMOS quadrature VCOs
  • On the phase-noise and phase-error performances of multiphase LC CMOS VCOs
  • Phase noise analysis of the LC-tank CMOS oscillator
• 2003
  • Highly functional tunnelling devices integrated in 3D
  • Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs
  • Serendipitous noise reduction in inductively degenerated CMOS RF LNAs
• 2002
  • A 2GHz Low-Phase-Noise CMOS quadrature VCO
  • A 2GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6° phase error
  • A 57-dB image band rejection CMOS GmC polyphase filter with automatic frequency tuning for Bluetooth
  • A low-phase-noise low-phase-error 1.8 GHz quadrature CMOS VCO
  • Analysis and design of a 1.8-GHz CMOS LC quadrature VCO
  • Bandwidth considerations for a CALLUM transmitter architecture
  • Circuits and devices with integrated VFETs and RTDs
  • On the use of Nauta's transconductor in low-frequency CMOS g(m)-C bandpass filters
  • Tail current noise suppression in RF CMOS VCOs
• 2001
  • A 1.8 GHz CMOS VCO with reduced phase noise
  • A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor
  • A 2.2 GHz CMOS VCO with inductive degeneration noise suppression
  • Noise optimization of an inductively degenerated CMOS low noise amplifier
  • Phase noise reduction in RF CMOS VCO's via capacitive filtering
  • Very low phase noise RF quadrature oscillator architecture
• 2000
  • A 1.8-GHz CMOS VCO tuned by an accumulation-mode MOS varactor
  • A 2.4-GHz CMOS monolithic VCO with an MOS varactor
  • A CMOS gm-C IF filter for Bluetooth
  • A CMOS gm-C polyphase filter with high image band rejection
  • A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier
  • On the use of MOS varactors in RF VCOs
• 1999
  • A 100MHz CMOS gm-C bandpass filter
  • A 2.4-GHz CMOS monolithic VCO based on an MOS varactor
  • A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
  • A digitally controlled shunt capacitor CMOS delay line
  • Extension of the Cochrun-Grabel method to allow for mutual inductances
  • Reactors - Circuit Theory and Silicon Integrated Applications
• 1998
  • A CMOS current amplifier for biological sensors
  • A Parasitic Insensitive Transconductance-C Bandpass Filter
  • A comparison between two 1.8GHz CMOS VCOs tuned by different varactors
  • Characteristic polynomial and zero polynomial with the Cochrun-Grabel method
  • Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution
• 1997
  • Chip for wideband digital predistortion RF power amplifier linearisation
• 1996
  • MHITIC: 8-channels, 1-ns, Multihit Time-to-Digital Converter CMOS Integrated Circuit
• 1995
  • Custom DSP Design of a GSM Speech Coder
• 1993
  • A GSM speech coder implemented on a customized processor architecture
  • Custom DSP design of a GSM speech coder
  • Custom DSP implementation of a GSM speech coder