Yasser Sherazi
Titel
Doktorand
Organisation
046-2229011
+46762323697
Yasser [dot] Sherazi [at] eit [dot] lth [dot] se
Publikationer (hämtat ur Lunds universitets publikationsdatabas)
författare
- 2013
- 2012
- A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
- A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
- A receiver architecture for devices in wireless body area networks
- Integration of Full-Custom Cells in a Standard-Cell Based Flow
- Sizing of Dual-VT Gates for Sub-VT circuits
- Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
- 2011
- Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
- Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
- Physical implementation of analog circuits assisted by conventional digital place and route methods
- Synthesis Strategies for Sub-VT Systems
- 2010
- 2009
