Erik Larsson

författare

• 2012
  • Access Time Analysis for IEEE P1687
  • Accessing Embedded DfT Instruments with IEEE P1687
  • An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
  • Fault management in an IEEE P1687 (IJTAG) environment
  • Re-using Chip Level DFT at Board Level
  • Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
  • Scheduling Tests for 3D Stacked Chips under Power Constraints
  • Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
• 2011
  • Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
  • Design Automation for IEEE P1687
  • European Test Symposium (ETS) 2011
  • Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
  • Measurement Point Selection for In-Operation Wear-Out Monitoring
  • Scheduling Tests for 3D Stacked Chips under Power Constraints
  • SoC-Level Fault Management based on P1687 IJTAG
  • Test Scheduling for 3D Stacked ICs under Power Constraints
  • Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
• 2010
  • A Distributed Architecture to Check Global Properties for Post-Silicon Debug
  • Checking Pipelined Distributed Global Properties for Post-silicon Debug
  • Checking Pipelined Distributed and Global Properties at Post-silicon Debug
  • Efficient Embedding of Deterministic Test Data
  • Efficient Embedding of Deterministic Test Data
  • Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
  • Energy-Efficient Redundant Execution for Chip Multiprocessors
  • Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
  • Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
  • Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
  • Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
  • On-line Techniques to Adjust and Optimize Checkpointing Frequency
  • Optimizing Fault Tolerance for Multi-Processor System-on-Chip
  • Power Constrained Test Scheduling for 3D Stacked Chips : (poster)
  • Scan Cells Reordering to Minimize Peak Power During Test Cycle :  A Graph Theoretic Approach
  • Scheduling Tests for Stacked 3D Chips under Power Constraints
  • Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
  • Test Scheduling of Modular System-on-Chip under Capture Power Constraint
  • Test Time Analysis for IEEE P1687
  • Test scheduling on IJTAG
  • Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
• 2009
  • An Even-Odd DFD Technique for Scan Chain Diagnosis
  • Capture Power Reduction for Modular System-on-Chip Test
  • Deterministic Scan-Chain Diagnosis for Intermittent Faults
  • Fault-Tolerant Average Execution Time Optimization for System-On-Chips
  • Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
  • Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
  • On Minimization of Peak Power for Scan Circuit during Test
  • On Scan Chain Diagnosis for Intermittent Faults
  • Power Efficient Redundant Execution for Chip Multiprocessors
  • Power-Aware System-Level DfT and Test Planning
  • Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
  • Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
• 2008
  • A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
  • An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
  • An Integrated System-on-Chip Test Framework
  • Core-Level Expansion of Compressed Test Patterns
  • Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
  • On Reduction of Capture Power for Modular System-on-Chip Test
  • SOC Test Optimization with Compression-Technique Selection
  • Test Response Compression for Diagnosis in Volume Production
  • Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
• 2007
  • A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
  • An Architecture for Combined Test Data Compression and Abort-on-Fail Test
  • Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
  • Extended STAPL as SJTAG Engine
  • Improved Scan Chain Diagnosis
  • Optimized Integration of Test Compression and Sharing for SOC Testing
  • Protocol Requirements in an SJTAG/IJTAG Environment
  • Protocol Requirements in an SJTAG/IJTAG Environment
  • Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
  • Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
  • What Impacts Course Evaluation?
• 2006
  • Combined Test Data Compression and Abort-on-Fail Test
  • Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
  • High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO
  • Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
  • System-on-chip test scheduling with reconfigurable core wrappers
• 2005
  • A Test Data Compression Architecture with Abort-on Fail Capability
  • Abort-on-Fail Based Test Scheduling
  • Boundary-Scan Test Control in the ATCA Standard
  • Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
  • Emerging strategies for resource-constrained testing of system chips
  • Introduction to Advanced System-on-Chip Test Design and Optimization
  • Multiple Constraints Driven System-on-Chip Test Time Optimization
  • Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
  • Remote Boundary-Scan System Test Control for the ATCA Standard
  • SOC Test Scheduling with Test Set Sharing and Broadcasting
  • Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
• 2004
  • A Technique for Optimization of System-on-Chip Test Data Transportation
  • An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
  • Core Selection Integrated in the SOC Test Solution Design-Flow
  • Defect-Aware SOC Test Scheduling
  • Efficient test solutions for core-based designs
  • Integrating Core Selection in the SOC Test Solution Design-Flow
  • Preemptive system-on-chip test scheduling
  • Student-oriented Examination in a Computer Architecture Course
• 2003
  • A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
  • An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
  • Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
  • Defect Probability-based System-On-Chip Test Scheduling
  • Optimal System-on-Chip Test Scheduling
  • SOC Test Time Minimization Under Multiple Constraints
  • System-on-Chip Test Scheduling based on Defect Probability
  • Test Resource Partitioning and Optimization for SOC Designs
• 2002
  • An Integrated Framework for the Design and Optimization of SOC Test Solutions
  • An Integrated Framework for the Design and Optimization of SOC Test Solutions
  • Integrated Test Scheduling, Test Parallelization and TAM Design
  • Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers
  • Power Constrained Preemptive TAM Scheduling
• 2001
  • An Integrated System-On-Chip Test Framework
  • System-on-Chip Test Parallelization Under Power Constraints
  • Test Scheduling and Scan-Chain Division Under Power Constraint
  • The Design and Optimization of SOC Test Solutions
• 2000
  • A Technique for Test Infrastructure Design and Test Scheduling
  • An Integrated System-Level Design for Testability Methodology An Integrated System-Level Design for Testability Methodology
  • System-on-Chip Test Bus Design and Test Scheduling
  • Test Infrastructure Design and Test Scheduling Optimization