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A methodology for arithmetic reduction of the static power consumption verified on filter architectures

Författare:
  • Peter Nilsson
Publiceringsår: 2008
Språk: Engelska
Sidor: 11-14
Publikation/Tidskrift/Serie: International Conference on Microelectronics ICM
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.

Sammanfattning

Abstract in Undetermined

In today's technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Simulations are done in a typical 130 nm technology. Based on the simulation results, the static power in a digital filter is estimated and compared for two different architectures, one bit-parallel respectively bit-serial architecture. The paper shows a substantial reduction of the static power consumption when bit-serial arithmetic is used. The paper also shows that the relative power reduction is strongly dependent on the used word length, i.e. the reduction is larger for longer word lengths. The reduction is dependent on the ratio between the arithmetic and the storage (the registers) as well. Architectures where the arithmetic dominates will show a larger reduction of the static power consumption. A static power reduction down to 37 % is shown for the bit-serial filter architecture and a reduction down to 7 % is shown in the arithmetic in the filter.

Nyckelord

  • Electrical Engineering, Electronic Engineering, Information Engineering

Övriga

The 20th International Conference on Microelectronics (ICM'08)
Published
  • Digital ASIC-lup-obsolete
  • Elektronikkonstruktion-lup-obsolete
  • ISBN: 978-1-4244-2369-9

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