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Energy-Efficient Redundant Execution for Chip Multiprocessors

In English

Författare

  • Pramod Subramanyan
  • Virendra Singh
  • Kewal K. Saluja
  • Erik Larsson

Summary, in English

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

Publiceringsår

2010

Språk

Engelska

Sidor

143-146

Publikation/Tidskrift/Serie

Proceedings of the 20th symposium on Great lakes symposium on VLSI

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

Great Lakes Symposium on VLSI (GLSVLSI'10), 2010

Conference date

2010-05-16 - 2010-05-18

Conference place

Providence, United States

Status

Published

ISBN/ISSN/Övrigt

  • ISBN: 978-1-4503-0012-4