A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration
Författare
Summary, in English
This paper presents a 2-dimension (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated-ring-oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~10.6ps) is improved by the 1st-order noise shaping of the GRO. Moreover, since all delay differences between X phases and Y phases can be used (rather than only the diagonal line of the 1-dimension architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65nm CMOS process and consumes 2.3mA from 1.0V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2ps, while the average latency time (within 2ns) is less than 1/6 of that in a standard Vernier TDC.
Avdelning/ar
Publiceringsår
2016-03-29
Språk
Engelska
Sidor
1019-1023
Publikation/Tidskrift/Serie
IEEE Transactions on Circuits and Systems II: Express Briefs
Dokumenttyp
Artikel i tidskrift
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Other Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- ime to digital converter (TDC)
- Gated-Ring-Oscillator (GRO)
- Vernier, 2-dimension (2-D)
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 1549-7747