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A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs

Publiceringsår: 2000
Språk: Engelska
Sidor: 13-16
Publikation/Tidskrift/Serie: The 2000 IEEE International Symposium on Circuits and Systems. Proceedings.
Volym: 3
Dokumenttyp: Konferensbidrag


Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW



  • Technology and Engineering
  • low-power electronics
  • application specific integrated circuits
  • clocks
  • pulse generators
  • multiplying circuits


2000 International Symposium on Circuits and Systems (ISCAS 2000)
Geneva, Switzerland
  • Elektronikkonstruktion
  • ISBN: 0-7803-5482-6

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