Silicon realization of an OFDM synchronization algorithm
Publikation/Tidskrift/Serie: The 6th IEEE International Conference on Electronics, Circuits and Systems, Proceedings of ICECS '99.
N this paper a hardware architecture for an OFDM synchronizer is presented. The proposed synchronization unit can be used in any OFDM system that uses a cyclic prefix. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where both time and frequency offset are estimated simultaneously. The synchronization unit also performs frequency correction, which means that no feedback to the analog parts is necessary. Although the algorithm is too complex to be implemented on today's most powerful standard DSP, a hardware architecture that is optimized for the algorithm can be implemented with moderate complexity. The unit contains 32 kbit RAM and 5000 gates and the sample rate is 25 Msamples/s
- Technology and Engineering
IEEE 6th International Conference on Electronics, Circuits and Systems (ICECS’99)
- ISBN: 0-7803-5682-9