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Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style

Publiceringsår: 1999
Språk: Engelska
Sidor: 873-878
Publikation/Tidskrift/Serie: Proceedings of the 36th ACM/IEEE conference on Design automation
Dokumenttyp: Konferensbidrag


Power consumption in clock of large high performance
VLSIs can be reduced by adopting Globally Asynchronous,
Locally Synchronous design style (GALS). GALS
has small overheads for the global asynchronous communication
and local clock generation. We propose
methods to a) evaluate the benefits of GALS and account
for its overheads, which can be used as the basis
for partitioning the system into optimal number/size of
synchronous blocks, and b) automate the synthesis of
the global asynchronous communication. Three realistic
ASICs, ranging in complexity from 1 to 3 million
gates, were used to evaluate GALS benefits and overheads.
The results show an average power saving of
about 70% in clock with negligible overheads.



  • Electrical Engineering, Electronic Engineering, Information Engineering


36th Design Automation Conference (DAC’99)
New Orleans, LA, USA
  • Elektronikkonstruktion
  • ISBN: 1-58133-109-7

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