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Optimization and implementation of a Viterbi decoder under flexibility constraints

Författare:
Publiceringsår: 2008
Språk: Engelska
Sidor: 2411-2422
Publikation/Tidskrift/Serie: IEEE Transactions on Circuits and Systems - I: Regular Papers
Volym: 55
Nummer: 8
Dokumenttyp: Artikel
Förlag: IEEE Press

Sammanfattning

This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

  • Vinnova
Published
  • Digital ASIC: Flexible Coding and Decoding for Wireless Personal Area Networks
Yes
  • Elektronikkonstruktion
  • Digital ASIC
  • Telecommunication Theory
© 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
  • ISSN: 1549-8328

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