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A 312-Mhz CT DS Modulator Using a SC Feedback DAC with Reduced Peak Current

Författare:
  • Martin Andersson (Assistant Professor)
  • Lars Sundström
Publiceringsår: 2007
Språk: Engelska
Sidor: 240-243
Publikation/Tidskrift/Serie: Proceedings of the 33rd European Solid State Circuits Conference
Dokumenttyp: Konferensbidrag
Förlag: IEEE Press

Sammanfattning

This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92MHz bandwidth with a 312MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

ESSCIRC
2007-09-11/2007-09-13
München, Germany
Published
Yes
  • ISSN: 1930-8833
  • ISBN: 978-1-4244-1125-2

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