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High-level design flow for all-digital PLLs

Författare:
Publiceringsår: 2006
Språk: Engelska
Sidor: 247-250
Publikation/Tidskrift/Serie: 24th Norchip Conference, 2006.
Dokumenttyp: Konferensbidrag

Sammanfattning

Deep-submicrometer CMOS processes are not suitable for traditional analog circuit design but they provide new opportunities of integrating complex digital functions. Within RF wireless communications, frequency synthesis stands out as a fundamental feature and novel digital solutions have been suggested for its implementation. Moving from an existing model, the goal of this paper is to outline the steps of a high-level approach to the design of an all-digital phase-locked loop (ADPLL)

Disputation

Nyckelord

  • Technology and Engineering

Övriga

2006-11-01
Linkoping
Published
Yes
  • ISBN: 1-4244-0772-9

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