Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

A digitally controlled shunt capacitor CMOS delay line

  • Pietro Andreani
  • Franco Bigongiari
  • Roberto Roncella
  • Roberto Saletti
  • Pierangelo Terreni
Publiceringsår: 1999
Språk: Engelska
Sidor: 89-96
Publikation/Tidskrift/Serie: Analog Integrated Circuits and Signal Processing
Volym: 18
Nummer: 1
Dokumenttyp: Artikel


Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 x 0.5 ns delay under large temperature, supply voltage, and technological process quality variations.



  • Electrical Engineering, Electronic Engineering, Information Engineering


  • ISSN: 0925-1030

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen