A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility

In English This paper discusses design and measurements of
a flexible Viterbi decoder fabricated in 130-nm digital CMOS.
Flexibility was incorporated by providing various code rates and
modulation schemes to adjust to varying channel conditions.
Based on previous trade-off studies, flexible building blocks were
carefully designed to cause as little area penalty as possible. The
chip runs down to a minimal core supply of 0.8V. It turns out that
striving for more modulation schemes is beneficial in terms of
power consumption once the price is paid for accepting different
code rates viz. radices in the trellis and survivor path units.