Test Resource Partitioning and Optimization for SOC Designs
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.
- Electrical Engineering, Electronic Engineering, Information Engineering
- core-based design
- resource floor-planning
- test access mechanism
- test scheduling
- TAM routing
2003 IEEE VLSI Test Symposium VTS03
- ISSN: 1093-0167
- ISBN: 0-7695-1924-5