Test Resource Partitioning and Optimization for SOC Designs
Författare
Summary, in English
Publiceringsår
2003
Språk
Engelska
Sidor
319-319
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- core-based design
- resource floor-planning
- test access mechanism
- TAM
- test scheduling
- TAM routing
Conference name
2003 IEEE VLSI Test Symposium VTS03
Conference date
2003-04-27 - 2003-05-01
Conference place
Napa, CA, United States
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 1093-0167
- ISBN: 0-7695-1924-5