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A coarse-grained dynamically reconfigurable architecture for digital signal processing

Publiceringsår: 2009
Språk: Engelska
Sidor: 4
Publikation/Tidskrift/Serie: 9th Swedish System-On-Chip Conference
Dokumenttyp: Konferensbidrag
Förlag: Swedish Chapter of IEEE Solid-State Circuits Society (SSCS)


This paper presents design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing the separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible static mapping of arbitrary applications, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality is demonstrated by mapping a radix 22 FFT processor reconfigurable between 32 and 1,024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to an ordinary DSP solution.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • DSP
  • CGRA


9th Swedish System-on-Chip Conference, SSoCC 2009
Arild, Sweden
  • Vinnova
  • Digital ASIC

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