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A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

Författare:
Publiceringsår: 2009
Språk: Engelska
Sidor: 289-292
Publikation/Tidskrift/Serie: Proc. 2009 IEEE Asia Pacific Microwave Conference, APMC 2009, Singapore
Dokumenttyp: Konferensbidrag
Övrig information: Best paper award Active circuits (APMC Price)

Sammanfattning

A 12 GHz PLL with digital output phase control
has been implemented in a 90 nm CMOS process. It is intended
for LO signal generation in integrated phased array transceivers.
Locally placed PLLs eliminate the need of long high frequency
LO routing to each transceiver in a phased array circuit.
Routing losses are thereby reduced and design of integrated
phased array transceivers become more modular. A chip was
manufactured, featuring two separate fully integrated PLLs
operating at 12 GHz, with a common 1.5 GHz reference. The chip,
including pads, measures 1050x700 μm2. Each PLL consumes
15 mA from a 1.2 V supply, with a typical measured phase noise
of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds
360.

Disputation

Nyckelord

  • Technology and Engineering
  • Phase locked loops
  • Beam steering
  • CMOS analog integrated circuits.
  • Array signal processing
  • Millimeter wave antenna arrays

Övrigt

Asia Pacific Microwave Conference, APMC 2009
2009-12-07
Singapore
  • Swedish Foundation for Strategic Research (SSF)
Published
  • Analog/RF Circuits Group: Analog Building Blocks and Architectures
Yes
  • Elektronikkonstruktion
  • Analog RF

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