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Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter

Författare:
Publiceringsår: 2009
Språk: Engelska
Dokumenttyp: Konferensbidrag
Förlag: IEEE

Sammanfattning

This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory
(RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes
prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II
Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.

Disputation

Nyckelord

  • Technology and Engineering
  • hardware implementation
  • faster-than-Nyquist
  • multicarrier
  • transmitter

Övriga

NORCHIP
2009-11-16/2009-11-17
Trondheim, Norway
  • Swedish Foundation for Strategic Research (SSF)
Published
  • EIT_HSWC:Coding Coding, modulation, security and their implementation
Yes
  • Telecommunication Theory
  • Digital ASIC
  • Elektronikkonstruktion
  • ISBN: 978-1-4244-4310-9

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