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A 5GHz 90-nm CMOS all digital phase-locked loop

Publiceringsår: 2009
Språk: Engelska
Sidor: 65-68
Dokumenttyp: Konferensbidrag

Sammanfattning

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.

Disputation

Nyckelord

  • Technology and Engineering
  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • All Digital Phase-Locked Loop (ADPLL)
  • Time-to-Digital Converter (TDC)
  • CMOS

Övriga

ASSCC
2009-11-18
Taiwan
Published
Yes
  • Elektronikkonstruktion
  • Analog RF
  • Data converters & RF

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