Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

A 5GHz 90-nm CMOS all digital phase-locked loop

Författare

Summary, in English

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • All Digital Phase-Locked Loop (ADPLL)
  • Time-to-Digital Converter (TDC)
  • CMOS

Conference name

IEEE Asian Solid-State Circuits Conference (ASSCC), 2009

Conference date

2009-11-16 - 2009-11-18

Conference place

Taiwan, Taiwan

Status

Published

Forskningsgrupp

  • Elektronikkonstruktion
  • Analog RF
  • Data converters & RF