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A <1 pJ sub-VT Cardiac Event Detector in 65 nm LL-HVT CMOS

Publiceringsår: 2010
Språk: Engelska
Sidor: 253-258
Publikation/Tidskrift/Serie: Proceedings of the 2010 18TH IEEE/IFIP International Conference on VLSI and System-on-Chip
Dokumenttyp: Konferensbidrag
Förlag: IEEE


This paper presents the hardware implementation
of a wavelet based event detector for cardiac pacemakers. A
high level energy estimation flow was applied to evaluate energy
efficiency of standard-cell based designs, over several CMOS
technology generations, from 180 to 65 nm, operated in the
sub-threshold domain. The simulation results indicate a 65 nm
low-leakage high-threshold (LL-HVT) CMOS technology as the favourable choice. Accordingly, the design was fabricated in 65 nm LL-HVT CMOS. Measurements validate the simulation results and prove that the circuit is fully functional down to a supply voltage of 250mV. At the energy minimum voltage of 320mV the circuit dissipates 0.88 pJ per sample at a clock rate
of 20 kHz.



  • Electrical Engineering, Electronic Engineering, Information Engineering


18th IEEE/IFIP International Conference on VLSI and System-on-Chip
Madrid, Spain
  • Vetenskapsrådet
  • Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers
  • Elektronikkonstruktion
  • Digital ASIC
  • ISBN: 978-1-4244-6469-2

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