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A 5GHz 90-nm CMOS all digital phase-locked loop

Författare

Summary, in English

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply.

Publiceringsår

2011

Språk

Engelska

Sidor

49-59

Publikation/Tidskrift/Serie

Analog Integrated Circuits and Signal Processing

Volym

66

Issue

1

Dokumenttyp

Artikel i tidskrift

Förlag

Springer

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • Time-to-Digital Converter (TDC)
  • All Digital Phase-Locked Loop (ADPLL)
  • CMOS

Status

Published

Forskningsgrupp

  • Analog RF
  • Data converters & RF

ISBN/ISSN/Övrigt

  • ISSN: 0925-1030