Meny

Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet

Författare:
  • Ping Lu (Dr.)
  • Yan Wang (Mr.)
  • Liang Li (Prof.)
  • Junyan Ren (Prof.)
Publiceringsår: 2006
Språk: Kinesiska
Sidor: 137-142
Publikation/Tidskrift/Serie: Journal of semiconductors
Volym: 27
Nummer: 1
Dokumenttyp: Artikel

Sammanfattning

This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump,and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Mbps modes.This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising (falling) edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs,thus greatly saving area and power.The data show that the σ of the voltage control oscillator jitter_ cycle-cycle is only 11ps while that of the reference clock jitter_ cycle-cycle is 16ps.This indicates that the frequency synthesizer works well for transmitters and receivers.The circuit is designed with SMIC 0.18μm standard CMOS technology,the power supply is 1.8V,and the power is lower than 4mW.

Disputation

Nyckelord

  • Technology and Engineering
  • Ethernet frequency synthesizer clock jitter

Övriga

Published
Yes
  • ISSN: 1674-4926

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen