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Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS

Publiceringsår: 2010
Språk: Engelska
Dokumenttyp: Konferensbidrag


This manuscript presents simulation results of energy
dissipation in sub-threshold (sub-VT ) of various 16-bit
adder structures. The architectures designed for the comparative
experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit
parallel adder structures. The designs are synthesized in a 65 nm
low-leakage high-threshold CMOS technology. The results show
that an energy minimum operating voltage exists for all the
three implementations, however the 8-bit digit serial has the least
energy minimum operating point. The advantage of the bit-serial
structure is that by employing this technique we may save 88%
area when compared to parallel implementation and 66% area
when compared to digital-serial implementation.



  • Technology and Engineering
  • Adder
  • sub-threshold
  • Energy Efficiency
  • sub-VT
  • 65 nm CMOS


Swedish System On Chip (SSoCC'10)
Vildmarkshotellet, Kolmården, Sweden
  • Elektronikkonstruktion
  • Digital ASIC

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