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A 1.1-Gb/s 115-pJ/bit configurable MIMO detector using 0.13-um CMOS technology

Författare:
Publiceringsår: 2010
Språk: Engelska
Sidor: 701-705
Publikation/Tidskrift/Serie: IEEE Transactions on Circuits and System-II
Volym: 57
Nummer: 9
Dokumenttyp: Artikel

Sammanfattning

This brief presents an efficient and configurable multiple-input–multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 $times$ 2/3 $times$ 3/4 $times$ 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13- $muhbox{m}$ single-poly- and eight-metal (1P8M) CMOS technology with a core area of 3.9 $hbox{mm}^{2}$. Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40% more energy efficient than state of the art in the open literature.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

Published
Yes
  • ISSN: 1549-7747

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