Modelling and optimization of III/V transistors with matrices of nanowires
Författare
Summary, in English
The magnitude and Impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated Simulations of the S parameters indicate an intrinsic f(T) of about 690 GHz for 50 nm L-G We show that f(T) reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes Finally the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators (C) 2010 Elsevier Ltd All rights reserved
Avdelning/ar
Publiceringsår
2010
Språk
Engelska
Sidor
1505-1510
Publikation/Tidskrift/Serie
Solid-State Electronics
Volym
54
Issue
12
Dokumenttyp
Artikel i tidskrift
Förlag
Elsevier
Ämne
- Condensed Matter Physics
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- Wrap gate
- InAs
- Ring oscillator
- Nanowire
- Field Effect Transistor
Status
Published
Forskningsgrupp
- Nano
ISBN/ISSN/Övrigt
- ISSN: 0038-1101