Double-edge-triggered D-flip-flop for high speed CMOS circuits

Summary, in English

Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology.

• Författare: Morteza Afgahi; Jiren Yuan
• Publiceringsår: 1991
• Språk: Engelska
• Sidor: 1168-1170
• Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
• Volym: 26
• Issue: 8
• Länkar: http://dx.doi.org/10.1109/4.90071
• Dokumenttyp: Artikel i tidskrift
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 0018-9200