An 8-Bit, 100-MHz low glitch interpolation DAC

Summary, in English

This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It includes a 16-tap voltage controlled delay line and 8-Bit based linear interpolators, making the effective clock rate up to 1.6-GHz. With the linear interpolation, the requirement on the analog reconstruction filter is relaxed, and low glitch digital to analog conversion is achieved. The chip is fabricated with a 3.3 V, 0.35 μm digital CMOS process

• Författare: Zhou Yijun; Jiren Yuan
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2001
• Språk: Engelska
• Sidor: 116-119
• Publikation/Tidskrift/Serie: Proceedings of the 2001 IEEE International Symposium on Circuits and Systems
• Volym: 4
• Länkar: http://dx.doi.org/10.1109/ISCAS.2001.922184
• Dokumenttyp: Konferensbidrag
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems, ISCAS, 2001
• Conference date: 2001-05-06 - 2001-05-09
• Conference place: Sydney, NSW, Australia
• Status: Published
• ISBN/ISSN/Övrigt: ISBN: 0-7803-6685-9