An embedded low power FIR filter

In English A new sampler with embedded FIR filter was designed with the charge sampling technique. The filter functions by summing the weighted current on a passive capacitor and the weighting factors are decided by the FIR coefficients. The performance of the filter can well compete with conventional analog filter but with smaller area and less power consumption. A testing chip was designed with 2 V supply, 7 mW power consumption and 0.4 mm2 area in 0.35 μm CMOS technology