An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

In English A complete architecture with transistor level simulation is
presented for a low power analog convolutional decoder in 65 nm CMOS.
The decoder core operates in the weak inversion (sub-VT) and realizes the
BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of
a (7,5) convolutional code. The complete decoder also incorporates serial
I/O digital interfaces and current mode differential DACs. The simulated
bit error rate is presented to illustrate the coding gain compared to an
uncoded system. Our results show that a low power, high throughput
convolutional decoder up to 1.25 Mb/s can be implemented using analog
circuitry with a total power consumption of 84 μW. For low rate
applications the decoder consumes only 47 μW at a throughput of 250
kb/s.