Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder
Författare
Summary, in English
Architectural improvements for a multicarrier
faster-than-Nyquist (FTN) decoder are presented in this work.
A previously designed FTN decoder has been optimized during
implementation, especially with respect to memory considerations
to reduce area and power. The memory optimized architecture
achieves 28.7% savings in overall chip area and provides 43.8%
savings in the estimated power compared to the pre-optimized
design. The BER performance tradeoff from one of the memory
optimization shows that the degradation is acceptable and can
actually provide better performance for certain scenarios. The
other memory optimization considers the minimal buffering
required within the interference canceller, resulting in memory
reduction close to 50% of what was previously reported. The
performance from the actual RTL implementation of the FTN
decoder is also presented in comparison with the floating and
fixed point benchmark performances.
faster-than-Nyquist (FTN) decoder are presented in this work.
A previously designed FTN decoder has been optimized during
implementation, especially with respect to memory considerations
to reduce area and power. The memory optimized architecture
achieves 28.7% savings in overall chip area and provides 43.8%
savings in the estimated power compared to the pre-optimized
design. The BER performance tradeoff from one of the memory
optimization shows that the degradation is acceptable and can
actually provide better performance for certain scenarios. The
other memory optimization considers the minimal buffering
required within the interference canceller, resulting in memory
reduction close to 50% of what was previously reported. The
performance from the actual RTL implementation of the FTN
decoder is also presented in comparison with the floating and
fixed point benchmark performances.
Avdelning/ar
Publiceringsår
2011
Språk
Engelska
Sidor
296-300
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- faster-than-Nyquist
- hardware implementation
- optimization
- iterative decoder
Conference name
IEEE Computer Society Annual Symposium on VLSI
Conference date
2011-07-04
Conference place
Chennai, India
Status
Published
Projekt
- EIT_HSWC:Coding Coding, modulation, security and their implementation
Forskningsgrupp
- Telecommunication Theory
- Digital ASIC
- Elektronikkonstruktion