An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE's (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.
- Electrical Engineering, Electronic Engineering, Information Engineering
- fault coverage
- defect probabilities
- embedded systems
2004 IEEE Asian Test Symposium ATS 2004
- ISSN: 1081-7735
- ISBN: 0-7695-2235-1