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Ultra low power hardware for computing squared euclidean distances

Publiceringsår: 2011
Språk: Engelska
Dokumenttyp: Konferensbidrag

Sammanfattning

Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 34% is shown compared to traditional designs. The paper also shows that the optimized design can be done completely ripple free, which leads to a reduction of the critical path to far more than half. The reduction in complexity leads to a reduction in power consumption. The ripple free design also leads to lower power consumption for two reasons: the rippling in itself leads to unnecessary glitches, which costs power and the shorter critical path enables a lower supply voltage, which reduces the power consumption as well.

Disputation

Nyckelord

  • Technology and Engineering

Övrigt

European Conference on Circuit Theory and Design (ECCTD 2011)
2011-08-29
Linköping, Sweden
Published
Yes
  • Digital ASIC

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