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Multicarrier Faster-than-Nyquist Signaling Transceivers: From Theory to Practice

Publiceringsår: 2011
Språk: Engelska
Sidor: 142
Dokumenttyp: Doktorsavhandling

Sammanfattning

The demand for spectrum resources in cellular systems worldwide has seen a tremendous escalation in the recent past. The mobile phones of today are capable of being cameras taking pictures and videos, able to browse the Internet, do video calling and much more than an yesteryear computer. Due to the variety and the amount of information that is being transmitted the demand for spectrum resources is continuously increasing. Efficient use of bandwidth resources has hence become a key parameter in the design and realization of
wireless communication systems. Faster-than-Nyquist (FTN) signaling is one such technique that achieves bandwidth efficiency by making better use of the available spectrum resources at the expense of higher processing complexity in the transceiver.

This thesis addresses the challenges and design trade offs arising during the hardware realization of Faster-than-Nyquist signaling transceivers. The FTN system has been evaluated for its achievable performance compared to the processing overhead in the transmitter and the receiver. Coexistence with OFDM systems, a more popular multicarrier scheme in existing and upcoming wireless standards, has been considered by designing FTN specific processing blocks as add-ons to the conventional transceiver chain. A multicarrier system capable of operating under both orthogonal and FTN signaling has been developed. The performance of the receiver was evaluated for AWGN and fading channels. The FTN system was able to achieve 2x improvement in bandwidth usage with similar performance as that of an OFDM system. The extra processing in the receiver was in terms of an iterative decoder for the decoding of FTN modulated signals. An efficient hardware architecture for the iterative decoder reusing the FTN specific processing blocks and realize different functionality has been designed. An ASIC implementation of this decoder was implemented
in a 65nm CMOS technology and the implemented chip has been successfully verified for its functionality.

Disputation

2012-01-19
10:15
E:1406, E-building, Ole Römers väg 3, Lund University, Faculty of Engineering
  • Gerhard Fettweis (Prof.)

Nyckelord

  • Technology and Engineering
  • iterative decoding
  • bandwidth efficient
  • Faster-than-Nyquist
  • hardware architecture
  • multicarrier

Övriga

  • Swedish Foundation for Strategic Research (SSF)
  • EIT_HSWC:Coding Coding, modulation, security and their implementation
  • Digital ASIC
  • Viktor Öwall (Docent)
  • ISSN: 1654-790X
  • ISBN: 978-91-7473-223-8

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