High-level design flow for all-digital PLLs
Publikation/Tidskrift/Serie: 24th Norchip Conference, 2006.
Deep-submicrometer CMOS processes are not suitable for traditional analog circuit design but they provide new opportunities of integrating complex digital functions. Within RF wireless communications, frequency synthesis stands out as a fundamental feature and novel digital solutions have been suggested for its implementation. Moving from an existing model, the goal of this paper is to outline the steps of a high-level approach to the design of an all-digital phase-locked loop (ADPLL)
- Electrical Engineering, Electronic Engineering, Information Engineering
- ISBN: 1-4244-0772-9