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Energy-Efficient Redundant Execution for Chip Multiprocessors

  • Pramod Subramanyan
  • Virendra Singh
  • Kewal K. Saluja
  • Erik Larsson
Publiceringsår: 2010
Språk: Engelska
Sidor: 143-146
Dokumenttyp: Konferensbidrag


Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.



  • Technology and Engineering


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