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Scheduling Tests for Stacked 3D Chips under Power Constraints

Publiceringsår: 2010
Språk: Engelska
Sidor: 4
Dokumenttyp: Konferensbidrag


This paper addresses test application time (TAT)
reduction for core-based stacked 3D chips. In contrast to the
traditional method of testing non-stacked chips where the same
test schedule is applied both at wafer test and at final test, stacked
3D chips need a pre-bond test schedule for each individual chip
and a different post-bond test schedule where all chips are jointly
tested. We consider a system of core-based chips where each core
is tested with a dedicated Built-In Self-Test (BIST) engine and
define an algorithm that defines each pre-bond test schedule and
the post-bond test schedule such that the overall TAT is
minimized and power constraints are met. The cost due to the
number of BIST control-lines is also taken into account.
Experiments with the proposed algorithm show significant savings
in TAT.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Built in Self Test (BIST)
  • Design for Test (DfT)
  • Test scheduling
  • Sessions
  • Test time
  • Test cost
  • 3D Stacked Integrated Circuit (SIC)
  • Through Silicon Via (TSV).


Swedish SoC Conference 2010
Kolmården, Sweden
  • Digital ASIC

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