Du är här

Power Efficient Redundant Execution for Chip Multiprocessors

  • Pramod Subramanyan
  • Virendra Singh
  • Kewal K. Saluja
  • Erik Larsson
Publiceringsår: 2009
Språk: Engelska
Sidor: 1-6
Dokumenttyp: Konferensbidrag


This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.



  • Technology and Engineering


Workshop on Dependable and Secure Nanocomputing
Lisbon, Portugal

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

LERU logotype U21 logotype

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen