Javascript is not activated in your browser. This website needs javascript activated to work properly.
Du är här

System-on-Chip Test Bus Design and Test Scheduling

Publiceringsår: 2000
Språk: Engelska
Dokumenttyp: Konferensbidrag


We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.



  • Technology and Engineering
  • testing
  • test scheduling
  • test bus infrastructure design
  • power consumption
  • simulated annealing


International Test Synthesis Workshop,2000

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen