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System-on-Chip Test Bus Design and Test Scheduling

Författare:
Publiceringsår: 2000
Språk: Engelska
Dokumenttyp: Konferensbidrag

Sammanfattning

We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.

Disputation

Nyckelord

  • Technology and Engineering
  • testing
  • test scheduling
  • test bus infrastructure design
  • power consumption
  • simulated annealing

Övriga

International Test Synthesis Workshop,2000
Published
Yes

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