System-on-Chip Test Bus Design and Test Scheduling
We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.
- Technology and Engineering
- test scheduling
- test bus infrastructure design
- power consumption
- simulated annealing
International Test Synthesis Workshop,2000