Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip

In English The increasingamount of test data needed to test SOC (System-on-Chip) entailsefficient design of the TAM (test access mechanism), which is usedto transport test data inside the chip. Having a powerful TAM willshorten the test time, but it costs large silicon area to implementit. Hence, it is important to have an efficient TAM with minimalrequired hardware overhead. We propose a technique that makes useof the existing bus structure with additional buffers inserted ateach core to allow test application to the cores and test datatransportation over the bus to be performed asynchronously. Thenon-synchronization of test data transportation and testapplication makes it possible to perform concurrent testing ofcores while test data is transported in a sequence. We haveimplemented a Tabu search based technique to optimize our testarchitecture, and the experimental results indicate that itproduces high quality results at low computationalcost.