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Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip

Författare:
Publiceringsår: 2005
Språk: Engelska
Sidor: 403-409
Dokumenttyp: Konferensbidrag
Förlag: IEEE Computer Society Press

Sammanfattning

The increasingamount of test data needed to test SOC (System-on-Chip) entailsefficient design of the TAM (test access mechanism), which is usedto transport test data inside the chip. Having a powerful TAM willshorten the test time, but it costs large silicon area to implementit. Hence, it is important to have an efficient TAM with minimalrequired hardware overhead. We propose a technique that makes useof the existing bus structure with additional buffers inserted ateach core to allow test application to the cores and test datatransportation over the bus to be performed asynchronously. Thenon-synchronization of test data transportation and testapplication makes it possible to perform concurrent testing ofcores while test data is transported in a sequence. We haveimplemented a Tabu search based technique to optimize our testarchitecture, and the experimental results indicate that itproduces high quality results at low computationalcost.

Disputation

Nyckelord

  • Technology and Engineering
  • testing
  • system-on-chip
  • test access mechanism
  • TAM
  • bus structure
  • test data transportation

Övriga

8th Euromicro Conference on Digital System Design DSD 2005
2005-08-30/2005-09-03
Porto, Portugal
Published
Yes
  • ISBN: 0-7695-2433-8

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