Du är här

An Integrated System-On-Chip Test Framework

Författare:
Publiceringsår: 2001
Språk: Engelska
Sidor: 138-144
Dokumenttyp: Konferensbidrag
Förlag: IEEE Computer Society Press

Sammanfattning

In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

Disputation

Nyckelord

  • Technology and Engineering
  • testing
  • system-on-chip
  • test access mechanism selection
  • test parallelization
  • test resource placement
  • power consumption
  • embedded systems

Övrigt

Design, Automation and Test in Europe DATE Conference
2001-03-13/2001-03-16
Munich, Germany
Published
Yes
  • ISSN: 1530-1591
  • ISBN: 0-7695-0993-2

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen

LERU logo U21 logo