A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS

Summary, in English

A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.

• Författare: Ping Lu; Pietro Andreani
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2010
• Språk: Engelska
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Länkar: http://dx.doi.org/10.1109/NORCHIP.2010.5669467
• Dokumenttyp: Konferensbidrag
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: NORCHIP Conference, 2010
• Conference date: 2010-11-15 - 2010-11-16
• Conference place: Tampere, Finland
• Status: Published
• ISBN/ISSN/Övrigt: ISBN: 978-1-4244-8972-5