A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
Additional info: Dear reviewer, I added pagers to the conference paper and its access link http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6271835&c... Could you please make my paper connected with this link?
This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in an improved Vernier TDC. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. Additionally, an automatic tuning bank controller selects the active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The equivalent in-band phase noise at 2.7GHz is -110dBc/Hz with a reference clock of 25MHz. The digital PLL is simulated in a 90nm CMOS process, indicating a current consumption of 21mA from a 1.2V supply.
- Technology and Engineering
- ISSN: 0271-4302