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A 0.13µm CMOS ΔΣ PLL FM Transmitter

Författare:
Publiceringsår: 2011
Språk: Engelska
Sidor: 4
Dokumenttyp: Konferensbidrag

Sammanfattning

A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.

Disputation

Nyckelord

  • Technology and Engineering

Övriga

Norchip
2011-11-14/2011-11-15
Lund, Sweden
Published
Yes
  • ISBN: 978-1-4577-0514-4

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