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Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Publiceringsår: 2012
Språk: Engelska
Sidor: 442-447
Dokumenttyp: Konferensbidrag
Förlag: IEEE Computer Society


Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.



  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Test Scheduling
  • 3D stacked IC
  • JTAG
  • Test Architecture
  • Through Silicon Via


2012 25th International Conference on VLSI Design
Hyderbad, India
  • Digital ASIC
© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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